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    Welcome to Digital Electronics Lab

    Welcome Everyone

    Dear students,

    Welcome to Digital Electronics Lab Course. I'm Md. Toukirul Hassan, will conduct this course and be a part of your learning throughout this course. I hope you will enjoy and enrich your knowledge in this course. We will dive into the depth of the topic in an easy manner and do our tasks properly.

    Thank you and let's start our learning...

    DElab_Course Outline

    Notice

     It's time for Lab Final VIVA...

    • TH

      Md. Toukirul Hassan

      Lecturer

      Department of Computer Science & Engineering

      Daffodil International University


      01749941655
      toukirul.cse0300.c@diu.edu.bd




      Course Rationale:

      Digital Electronics Lab is helpful for the students to acquire the basic knowledge of digital logic levels and their application to construct digital electronics circuits. This course will prepare students to perform the analysis and design of various digital electronic circuits.

      Course Objective:

      This course will enable a student to have a thorough understanding of the fundamental concepts and techniques used in digital electronics. It will also help the students to understand and examine the structure of various number systems and its application in digital design. The student can analyze and design various combinational and sequential circuits in this lab.

      Course Outcomes (CO’s):

      CO1

      Basic knowledge on logic gate implementation and get familiar with IC.

      CO2

      Understanding different combinational circuits and design circuits.

      CO3

      Able to solve problem using sequential circuit and logic design.

      Grading Scheme:

      Attendance: 10
             Lab Report : 20%
             Lab Performance: 30%
             Final Exam (Project + Project Report): 40%

      Textbook:

      1. Digital Systems-Principles and Application- Tocci (10th Edition)

      2. Digital Fundamentals- Floyd(8th Edition)

      Reference Books:

      1. Digital Logic Design – Morris Mano (5th Edition)

    • ATTENDANCE

    • Announcements Forum
      If there is any notice or any other important announcement, you will find it here.

  • Let's Start...





    • Course Outline

           (Click Here)

    • Lab Manual
         (click here)

    • tinkercad

      Online Simulator

      (Click and Create a profile here)

      Tinkercad is a free, online 3D modeling program that runs in a web browser, known for its simplicity and ease of use. Since it became available in 2011 it has become a popular platform for creating models for 3D printing as well as an entry-level introduction to Circuit Design.
    • Online Class Recording [Sec:O14] Page
      Restricted Not available unless: You belong to CSE224_[O14]
    • Online Class Recording [Sec:PC-F] Page
      Restricted Not available unless: You belong to CSE224_[PC - F&old]
    • Online Class Recording [Sec:PC-G] Page
      Restricted Not available unless: You belong to CSE224_[PC-G]

  • WEEK 1 Introduction to logic gates





    • Topics for Week 1

      Lab Task 1 

      ·   Get familiar with IC.
      .   Introduction to Basic Logic gates.

      Expected Outcome:

      ·    Able to implement the basic logic circuit using basic logic gates.


      Book Chapter:

      ·   Chapter 2, Digital Logic Design –By  Morris Mano.

    • View Class in this video:



    • Discussion on Lab1 (PC-G) Forum
      Restricted Not available unless: You belong to CSE224_[PC-G]
    • Discussion on Lab1 (PC-F) Forum
      Restricted Not available unless: You belong to CSE224_[PC - F&old]
    • Discussion on Lab 1 (O14) Forum
      Restricted Not available unless: You belong to CSE224_[O14]
    • Lab Report -01 Assignment
      Restricted Not available unless: You belong to any group

  • WEEK 2 Universal Logic Gates





    • Topics for Week 2

      Lab Task 2 

      ·    Universality of NAND and NOR gates, an implementation using universal gates.

      Expected Outcome:

      ·    Able to implement the logic circuit using universal gates.


      Book Chapter:

      ·   Chapter 2, Digital Logic Design –By  Morris Mano.

    • Lab-2 | Task-2:(See videos)

       

    • Lab Report-2 (Universal Logic Gates) Assignment
      Restricted Not available unless: You belong to any group

  • WEEK 3 Parity Generator & Checker





    • Topics for Week 3

      Lab Task 3

      ·    XOR, XNOR Gates
      .    Parity Generator and parity Checker Circuits

      Expected Outcome:

      ·    Able to implement the XOR, XNOR Gates, Parity Generator and parity Checker Circuits


      Book Chapter:

      ·   Chapter 2, Digital Logic Design –By  Morris Mano.

    • Task:3| See the videos and prepare for next class:

      Part-1:

      Part-2:

      Part-3:


  • WEEK 4 Assessment 1





    • 1. Boolean function to Logic gate
      2. Implement Universal Gate using basic gate 
      3. Parity Generator

    • Game: Basic Components in DE Interactive Content

      Dear all,
      It's a simple game!!!! Just Play... It may relieve your stress before the midterm exam.
      Game Instructions: You have to find a similar component pair. 

    • Quiz-1

      Here you will face a few basic questions.

  • WEEK 5 Half Adder





  • WEEK 6 Mid Term Examination






  • WEEK 7 Full Adder





    • Topics for Week 7 :

      Lab Task - 6

      ·    Full-adder Circuits Using Basic Logic Gates 

      Expected Outcome:

      ·    Able to implement Full adder 
      .    Able to implement binary adder


      Book Chapter:

      ·   Chapter 4, Digital Logic Design –By  Morris Mano.

    • View Lab-6 video:


    • Submit Your Lab Project Idea 

      • Form a group, not more than 3 members
      • Submit Project title, Group members Name, ID, Summary of your Idea in a pdf file.
      • You are requested to maintain your knowledge, integrity, innovation, and wisdom.

  • This topic

    WEEK 8 Encoder & Decoder





    • Topics for Week 8

      Lab Task  7:

      ·    Design and Implementation of an Encoder Using Basic Logic Gates

      ·    Design and Implementation of Decoder Circuits Using Logic Gates

      Expected Outcome:

      .    Exercise on encoder and decoder


      Book Chapter:

      ·   Chapter 4, Digital Logic Design –By  Morris Mano.

    • Video on Encoder & Decoder:


    • Lab Report -7 Assignment

       Encoder & Decoder 

  • WEEK 9 Full-adder from Decoder





    • Topics for Week 9

      Lab Task - 8 :

      ·    Design and Implementation of 3-to-8 Decoder Circuits Using Logic Gates

      .    Implement Full-adder from 3-to-8 decoder

      Expected Outcome:

      ·    Able to implement Full adder from decoder
      .    Exercise on decoder


      Book Chapter:

      ·   Chapter 4, Digital Logic Design –By  Morris Mano.

    • Video: Full-adder from 3-to-8 Decoder


    • Lab Report 8 Assignment
      Make a submission
      Submit Only Screenshot from tinkercad.

  • WEEK 10 Multiplexer





    • Topics for Week 10

      Lab Task  9:

      ·    Design and Implementation of Multiplexers

      .    Implement Multiplexer from boolean expression

      Expected Outcome:

      .    Able to implement Multiplexer


      Book Chapter:

      ·   Chapter 4, Digital Logic Design –By  Morris Mano.

    • Video: Multiplexer | 2-to-1 & 4-to-1 | Logic function


    • Lab Report- 9 Assignment
      Make a submission

      Submit only Screenshot from Tinkercad

  • WEEK 11 SR Latch





    • Topics for Week 11

      Lab Task  10 :

      ·    Realization of SR Latch using Integrated Circuit (IC) (NAND and NOR) Gates

      Expected Outcome:

      .    Able to implement sequential circuit
      .    Able to implement S-R Latch using NAND/NOR Gates


      Book Chapter:

      ·   Chapter 4, Digital Logic Design –By  Morris Mano.

    • Video: S-R Latch | Using NAND | Using NOR 


    • Lab Report - 10 Assignment
      Make a submission

      Submit only Screenshot from Tinkercad

  • WEEK 12 Lab Final Exam & Project Presentation






    • Lab Final & Project Presentation (require 2 classes)

      For Lab Final:

      1. Prepare the tinkercad profile with all completed tasks.
      2. Attend VIVA (formal)

      For Project:

      1. Project 
      2. Project Documentation (in PowerPoint presentation)
      3. Presentation (formal)


    • Important Dates and Tasks:
      Important dates

    • Project Presentation

    • Submit your Project Presentation Slide here: Assignment

      Anyone from each group must submit the ppt file before presentation day.

      File size must be less than 10MB.

    • Generate Project Link from Tinkercad &
      Submit Your Project Link here:

      Click to Submit Project
       

  • WEEK 13 Final Examination






  • Course Completion





    • Dear Students,

      After Completing all your tasks, Mid & Final exam, at the end of the whole course, you need to mark it as done.