Topic outline

  • Welcome to Digital Electronics

    cover

    Dear Students,

    Welcome to the Spring 2021 Semester!

    Hope you all are safe in this pandemic situation. We are waiting to see our beloved green campus. I am here to help you all as per your needs. 

    We will cooperate each other to do something better.


  • Let's Started


    • Course Rationale

      Digital Electronics course provides an introduction to the control of engineering systems using programmable logic, with specific focus on programmable logic devices. Within this context it introduces the fundamentals of digital logic, digital arithmetic, programmable logic and computer architecture. Research skills and aspects of professional practice are developed through group-based assignments. It emphasizes on techniques to design, analyse, plan, and implement complex digital systems.

      Course Objective

      The goal is to teach independently or work in a team to build simple logic circuits using basic gates as well as able to simplify Boolean functions by using the basic Boolean properties. Another goal is to teach how to design simple combinational logics using basic gates and to optimize Boolean logic using Karnaugh maps, even considering "don't care" condition. The course will also introduce the basic sequential logic components: SR Latch, D Flip-Flop and their usage and make the students able to analyse sequential logic circuits.

      Course Outcomes (CO’s)

      CO1

      Able to perform the conversion among different number systems. Be introduced to basic logic gates- AND, OR and NOT, XOR, XNOR and be able to build simple logic circuits using basic gates.

      CO2

      To implement the basic properties of Boolean algebra to simplify Boolean functions and construct circuits from them.

      CO3

      Able to minimize the Boolean functions using Karnaugh maps and “don’t care” condition. Consequently a student can then design any combinational circuits based on the real life scenarios.

      CO4

      To learn basic sequential logic components such as SR Latch, D Flip-Flop, JK Flip-Flop and their usage.


      Grading Scheme

      Class_Attendance : 7%
      Class Test/Quiz: 15%
      Class_Assignment: 5%
       Presentation (Using Video/ppt): 8%
      Midterm Exam: 25%
      Final Exam: 40%

      (Attendance: will be based on class attendance and weekly feedback; 
      Class Test: will be based on BLC online Test;
       Assignment and Presentation: Based on individual work;
      Mid and Final Exam: Open book, case studies;)

    • Academic Honesty

      1. Ensure Plagiarism <15%.
      2. Reflect Self Understanding.
      3. Avoid all unfair means to ensure growth of your positive mindset.

    • Course Outline Page
    • Reference Text Book Folder

      Textbook

              1. Digital Systems-Principles and Application- Tocci (10th Edition)

      2. Digital Fundamentals- Floyd(8th Edition)

      Reference Books

              1. Digital Logic Design – Morris Mano (5th Edition)


    • Quick Access Activities 

      Assignment 
      Presentation
      WEEK: WK1, WK2, WK3, WK4, WK5, WK6, WK7, WK8, WK9, WK10, WK11, WK12, WK13, WK14

  • Week 1: Introduction



    • Week 1: Introduction


      Topics of discussion:

      Lesson 1 

      ·       Introduction to the word “Digital” and Number System Conversions.
       ·        BCD (Binary Coded Decimal) Code.

      Expected Outcome:
      ·        Able to perform the conversion among different number systems.

      Book Chapter:
      ·  Chapter 1, Digital Logic Design –By  Morris Mano.

    • Lecture Materials 

      1. Number System .ppt

    • Exercise: 

      1. Convert the binary number 1101101001110101 to hex. 

      2. Convert the hex number D8C7 to binary. 

      3. 10101101 in binary is equal to ______ in hexadecimal and ______ in decimal.

      4. 101 in octal is equal to _____ in decimal and ______ in hexadecimal.


    • Weekly Discussion Forum
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    • Video of week 1 URL
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    • Weekly Discussion Forum
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    • Video of week 1 URL
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  • Week 2: Logic Gate



    • Week 2: Logic Gate


      Topics of discussion:

      Lesson 2

      ·  Error detecting code (Parity bit)
      ·  Boolean Algebra and Logic Gates

      Expected Outcome:
      ·  Be introduced to basic logic gates- AND, OR and NOT, XOR, XNOR  and a ble to build simple logic circuits .

      Book Chapter:
      ·  Chapter 2, Digital Logic Design –By  Morris Mano.

    • Lecture Materials 

      1. Boolean Algebra

    • Exercise on Lecture-2 Assignment
      View Make a submission

      Design circuit from following Boolean expressions.


    • Weekly Discussion Forum
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    • Video of week 2 URL
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    • Weekly Discussion Forum
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    • video of week 2 URL
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  • Week 3: Standard Forms



    • Week 3: Standard Forms


      Topics of discussion:

      Lesson 3

      ·  Boolean Function simplification and Standard Forms.
      ·  Implementing circuit from Boolean expression.

      Expected Outcome:
      ·  A ble to solve simple boolean function based logical and mathematical problems .

      Book Chapter:
      ·  Chapter 2, Digital Logic Design –By  Morris Mano.

    • Lecture Materials 

      1. Standard Forms

    • Lecture-3 exercise Assignment

      Design circuit form Boolean expression using three variables.

      A'B'C + AB'C' + AB'C + ABC' + ABC
    • Weekly Discussion Forum
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    • Video of week 3 URL
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    • Weekly Discussion Forum
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    • Video of week 3 URL
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  • Week 4: Universal gate



    • Week 4: Universal Gate


      Topics of discussion:

      Lesson 4

      ·  Universality of NAND and NOR gates, an implementation using universal gates.

      .  K-map Basic

      Expected Outcome:
      ·  A ble to solve logical and mathematical problems of universal gates.

      Book Chapter:
      ·  Chapter 3, Digital Logic Design –By  Morris Mano.

    • Lecture Materials 

    • Universal gate File
    • K-Map File
    • Weekly Discussion Forum
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    • video of week 4 URL
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    • Weekly Discussion Forum
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    • Video of week 4 URL
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  • Quiz 1

    • Quiz 1
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    • Quiz 1
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  • Week 5: K-Map



    • Week 5: K-Map


      Topics of discussion:

      Lesson 5

      ·  Simplification of Boolean Expression using Karnaugh maps (K-Map).

      Expected Outcome:
      ·   Able to minimize the Boolean functions using Karnaugh maps and “don’t care” condition.

      Book Chapter:
      ·  Chapter 4, Digital Logic Design –By  Morris Mano.

    • K-Map Exercise submission Assignment
      View Make a submission

      Solve question no 5 and 10 from exercise of K-Map.

    • K-MAP slide File
    • Weekly Discussion Forum
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    • Video of week 5 URL
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    • Weekly Discussion Forum
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    • Video of week 5 URL
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  • Week 6: Adder and Subtractor



    • Week 6: Adder and Subtractor


      Topics of discussion:

      Lesson 6 

      ·  Designing Combinational Circuits: Adder Circuit (Half and Full)
      ·  Subtractor Circuit
      Expected Outcome:
      ·  A  student able to design any combinational circuits based on the real life scenarios.
      .  Discuss on arithmetic and logical functions

      Book Chapter:
      ·  Chapter 5, Digital Logic Design –By  Morris Mano.

    • Lecture Materials 

      1. Binary Adder, Subtractor 


    • Self-Test


    • Weekly Discussion Forum
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    • Video of week 6 URL
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    • Weekly Discussion Forum
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    • Video of week 6 URL
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  • Quiz 2

    • Quiz 2
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    • Quiz 2
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  • Week 7 : MID Term Exam


    • Midterm Exam Answer Submission Assignment
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    • Midterm Exam Answer Submission Assignment
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    • Mid Syllabus: W1-W6

      1. Number Conversion 

      2. BCD Number System

      3.  Logic gate (Basic and Universal Logic Gate)

      4. Standard Forms

      5. K-Map

      6. Boolean Function Simplification

      7. Truth Table to Circuit (Combinational Circuit)

      8. Half Adder and Full Adder



      Instructions:

      * You need to download (1) ExamPaper.pdf (Question) and (2) Midterm Answer Script.doc.

      * Save your answer script as pdf with your ID e.g. CSE223-O1-192-15-12345-mid.pdf (Course Code-Section-Student ID)

      * No copy text or code or any from Internet as this will be detected by DIU BLC system plagiarism checker and this will lead to negative marking by the system.

       Best of Luck

  • Week 8: Decoder



    • Week 8: Decoder


      Topics of discussion:

      Lesson 8

      ·  Decoder (Definition, Truth Table, Block Diagram, Circuit Diagram, Implementation)
      .  Full adder from Decoder
      .  Half-Adder from Decoder

      Expected Outcome:
      ·  A  student can consequently design data transmission circuits as decoder.

      Book Chapter:
      ·  Chapter 5, Digital Logic Design –By  Morris Mano.

    • Lecture Materials 

      1. Decoder

    • Weekly Discussion Forum
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    • Video of Week 8 URL
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    • Weekly Discussion Forum
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    • Video of week 8 URL
      Restricted Not available unless: You belong to PC-R

  • Week 9: Encoder



    • Week 9: Encoder


      Topics of discussion:

      Lesson  9

      ·  Encoder (Definition, Truth Table, Block Diagram, Circuit Diagram, Implementation) 
      ·  Priority Encoder

      Expected Outcome:
      ·  A  student can consequently design data transmission circuits as Encoder.

      Book Chapter:
      ·  Chapter 5, Digital Logic Design –By  Morris Mano.

    • Lecture Materials 

      1. Encoder

    • Weekly Discussion Forum
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    • Video of week 9 URL
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    • Weekly Discussion Forum
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    • Video of week 9 URL
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    • Reference Materials


      1.

      2.

  • Presentation

    • Submit your presentation URL
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    • Submit your presentation URL
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  • Week 10: Multiplexer



    • Week 10: Multiplexer

      Topics of discussion:

      Lesson  10

      ·  Multiplexer (Definition, Truth Table, Block Diagram), 
      .   Function Implementation using Multiplexer

      .  Review data transmission circuits

      Expected Outcome:
      ·  A  student can consequently design data transmission circuits as Multiplexer.
      .  Perform exercise on circuit implementation to transmit data

      Book Chapter:
      ·  Chapter 5, Digital Logic Design –By  Morris Mano.

    • Lecture Materials 

      1. Multiplexer_Task

      2. MUX Example 

    • Self-Test 


    • Weekly Discussion Forum
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    • Video of week 10 URL
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    • Weekly Discussion Forum
      Restricted Not available unless: You belong to PC-R
    • Video of week 10 URL
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  • Week 11: SR Latch and Flip Flop



    • Week 11: SR Latch and Flip-Flop

      Topics of discussion:

      Lesson  11

      ·  Introduction to Sequential Circuits (Latch with NAND and NOR) 
      .  Discuss on Sequential and Combinational Circuit

      .  Introduction to SR flip flip
      .  Discuss on Sequential design

      Expected Outcome:
      ·  A  student can sequential circuit.
      .  Perform exercise on circuit implementation latch.
      .  Exercise on Sequential and Combinational Circuit

      Book Chapter:
      ·  Chapter 6, Digital Logic Design –By  Morris Mano.

    • Reference Video Tutorial URL

      SR Latch: This is easy to understand

    • Weekly Discussion Forum
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    • Video of week 11 URL
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    • Weekly Discussion Forum
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    • Video of week 11 URL
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  • Week 13: Review Class



    • Review Class

      Topics of discussion:

      Lesson  13

      - Decoder
      - Applications of Decoder
      - Encoder
      - Multiplexer
       - Flip Flop
      - Applications of Multiplexer

  • Week 14: Final Exam


    • Final Exam Syllabus: W6-W11

      1. Truth Table to Circuit (Combinational Circuit and Sequential Circuit)

      2. Half Adder and Full Adder

      3. Decoder 

      4. Encoder

      5. Multiplexer (MUX)

      6. SR latch, SR, JK Flip Flop


      Instructions:

      * You need to download (1) ExamPaper.pdf (Question) and (2) FinalExam Answer Script.doc.

      * Save your answer script as pdf with your ID e.g. CSE223-O1-192-15-12345-mid.pdf (Course Code-Section-Student ID)

      * No copy text or code or any from Internet as this will be detected by DIU BLC system plagiarism checker and this will lead to negative marking by the system.

       Best of Luck

    • Final Exam Answer Submission Assignment
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    • Final Exam Answer Submission Assignment
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