Section: Week 4: Assessment 1 | Digital Electronics Lab (Fall 2022) | DIU-BLC

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CSE Fall 2022

Amir Sohel

Nusrat Jahan (NJ)

Section outline

- Select activity Label
  
  Students must
  
  Mark as done
  
  Week 4: Viva 1
  
  1. Boolean function to Logic gate
  2. Implement Universal Gate using basic gate
  3. Parity Generator
  4. Adder
  
  Section Name Date
  Section O1 +R1 22.10.2020
  Section O2 25.10.2020
  Section O3 19.10.2020
  Section O4 26.10.2020